TITLE
MODELING AND IMPLEMENTATION OF AN AVR MICROCONTROLLER ARCHITECTURE
AUTHOR(S)
Ilian Varbov*, Petar Minev, Matyo Dinev, Valentina Kukenska
ABSTRACT
This paper presents the modeling and implementation of an AVR microcontroller architecture based on the ex-tended avre core. The main structural components of the model are described, including the program counter, program and data memory, register file, arithmetic logic unit (ALU), control unit, and status register. The modeling process employs the RTL approach and the VHDL hardware description language. The model is simulated in the ISim environment, demonstrating arithmetic, logic, and conditional branch instructions. Synthesis and implemen- tation were performed on a Spartan-3E (Basys 2) FPGA board, confirming the correct operation of the developed architecture. The proposed model is suitable for educational and research purposes.
DOI
How to cite this article:
Ilian Varbov*, Petar Minev, Matyo Dinev, Valentina Kukenska, MODELING AND IMPLEMENTATION OF AN AVR MICROCONTROLLER ARCHITECTURE, UNITECH – SELECTED PAPERS - 2025